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CY7C130/CY7C131 CY7C140/CY7C141
1K x 8 Dual-Port Static RAM
Features
* True Dual-Ported memory cells which allow simultaneous reads of the same memory location * 1K x 8 organization * 0.65-micron CMOS for optimum speed/power * High-speed access: 15 ns * Low operating power: ICC = 110 mA (max.) * Fully asynchronous operation * Automatic power-down * Master CY7C130/CY7C131 easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141 * BUSY output flag on CY7C130/CY7C131; BUSY input on CY7C140/CY7C141 * INT flag for port-to-port communication * Available in 48-pin DIP (CY7C130/140), 52-pin PLCC and 52-pin TQFP * Pin-compatible and functionally equivalent to IDT7130/IDT7140
Functional Description
The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). Two flags are provided on each port, BUSY and INT. BUSY signals that the port is trying to access the same location currently being accessed by the other port. INT is an interrupt flag indicating that data has been placed in a unique location (3FF for the left port and 3FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CY7C130 and CY7C140 are available in 48-pin DIP. The CY7C131 and CY7C141 are available in 52-pin PLCC and PQFP.
Logic Block Diagram
R/WL CEL OEL R/WR CER OER
Pin Configurations
DIP Top View
CE L R/W L BUSY L INTL OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 12 7C130 37 13 7C140 36 14 35 15 34 16 33 17 32 18 31 30 19 20 29 28 21 22 27 23 26 24 25 VCC CER R/WR BUSY R INTR OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R C130-2
I/O7L I/O0L [1] BUSYL A 9L A 0L
I/O CONTROL
I/O CONTROL
I/O7R I/O0R BUSYR
ADDRESS DECODER
MEMORY ARRAY
ADDRESS DECODER
A 9R A 0R
CEL OEL R/WL
ARBITRATION LOGIC (7C130/7C131 ONLY) AND INTERRUPT LOGIC
CER OER R/WR INTR
[2] INTL
[2]
C130-1
Notes: 1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor CY7C140/CY7C141 (Slave): BUSY is input. 2. Open drain outputs: pull-up resistor required.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 May 1989 - Revised May 29, 1997
CY7C130/CY7C131 CY7C140/CY7C141
Pin Configuration (continued)
PLCC Top View
BUSY R INTR NC BUSYL R/W L CEL VCC CER R/W R A0L OEL NC INT L A0L OEL NC INT L
PQFP Top View
BUSY R INTR NC BUSYL R/W L CEL VCC CER R/W R
A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L
8 9 10 11 12 13 14 15 16 17 18 19 20
7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C131 40 7C141 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O4L I/O5L I/O6L I/O7L NC GND
OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R
52 5150 49 48 47 4645 44 43 42 41 40 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R C130-4 NC GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
7C131 7C141
C130-3
1415 16 17 18 19 20 21 22 23 24 25 26
I/O4L I/O5L
Selection Guide
7C131-15 7C141-15 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) Com'l/Ind Military Com'l/Ind Military 75 65 65 15 190
[3]
7C131-25 7C141-25 25 170
[3]
7C130-30 7C131-30 7C140-30 7C141-30 30 170
I/O6L I/O7L
7C130-35 7C131-35 7C140-35 7C141-35 35 120 170 45 65
7C130-45 7C131-45 7C140-45 7C141-45 45 120 170 45 65
7C130-55 7C131-55 7C140-55 7C141-55 55 110 120 35 45
Shaded area contains preliminary information.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage to Ground Potential (Pin 48 to Pin 24) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -3.5V to +7.0V Output Current into Outputs (LOW) ............................. 20 mA
Notes: 3. 15 and 25-ns version available only in PLCC/PQFP packages. 4. TA is the "instant on" case temperature
Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA
Operating Range
Range Commercial Industrial Military[4] Ambient Temperature 0C to +70C -40C to +85C -55C to +125C VCC 5V 10% 5V 10% 5V 10%
2
CY7C130/CY7C131 CY7C140/CY7C141
Electrical Characteristics Over the Operating Range[5]
7C131-15[3] 7C141-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Output Short Circuit Current[7, 8] VCC Operating Supply Current Standby Current Both Ports, TTL Inputs Standby Current One Port, TTL Inputs Standby Current Both Ports, CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND CE = VIL, Outputs Open, f = fMAX[9] CEL and CE R > VIH, f = fMAX[9] Com'l Mil Com'l Mil 135 115 75 65 -5 -5 Test Conditions VCC = Min., IOH = -4.0 mA IOL = 4.0 mA IOL = 16.0 mA
[6]
7C130-30[3] 7C131-25,30 7C140-30 7C141-25,30 Min. 2.4 Max.
7C130-35,45 7C131-35,45 7C140-35,45 7C141-35,45 Min. 2.4 Max.
7C130-55 7C131-55 7C140-55 7C141-55 Unit Min. 2.4 Max. V 0.4 0.5 2.2 V 0.8 -5 -5 +5 +5 -350 110 120 35 45 75 90 15 15 mA mA mA V A A mA mA V
Min. 2.4
Max.
0.4 0.5 2.2 0.8 +5 +5 -350 190 -5 -5 2.2
0.4 0.5 2.2 0.8 +5 +5 -350 170 -5 -5
0.4 0.5 0.8 +5 +5 -350 120 170 45 65 90 115
ISB1
ISB2
CEL or CER > V IH, Com'l Active Port OutMil puts Open, [9] f = fMAX Both Ports CEL Com'l and CER > Mil VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0 One Port CEL or Com'l CER > VCC - 0.2V, Mil VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX[9]
ISB3
15
15
15 15
ISB4
Standby Current One Port, CMOS Inputs
125
105
85 105
70 85
mA
Shaded area contains preliminary information. Notes: 5. See the last page of this specification for Group A subgroup testing information. 6. BUSY and INT pins only. 7. Duration of the short circuit should not exceed 30 seconds. 8. This parameter is guaranteed but not tested. 9. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V.
Capacitance[8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 15 10 Unit pF pF
3
CY7C130/CY7C131 CY7C140/CY7C141
]
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIGAND SCOPE Equivalent to: OUTPUT R2 347 R1 893 5V OUTPUT 5 pF INCLUDING JIGAND SCOPE R2 347 BUSY OR INT R1 893 5V 281
30 pF (b) 3.0V GND 10%
C130-5
(a) THEVENIN EQUIVALENT 250 1.40V
ALL INPUT PULSES 90% 90% 10%
BUSY Output Load (CY7C130/CY7C131 ONLY)
C130-6
5 ns
5ns
Switching Characteristics Over the Operating Range[5,10]
7C131-15 7C141-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid[11] Data Hold from Address Change CE LOW to Data Valid[11] OE LOW to Data Valid
[11] [3]
7C130-25[3] 7C131-25 7C140-25 7C141-25 Min. 25 Max.
7C130-30 7C131-30 7C140-30 7C141-30 Min. 30 Max. Unit ns 30 0 30 20 3 15 5 15 0 25 30 25 25 2 0 25 15 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 0 ns ns
Description
Min. 15
Max.
15 0 15 10 3 10 3 10 0 15 15 12 12 2 0 12 10 0 10 0 0 25 20 20 2 0 15 15 0 0 5 3 0
25 25 15 15 15 25
OE LOW to Low Z[8,12, 13] OE HIGH to High Z[8,12, 13] CE LOW to Low Z
[8,12, 13]
CE HIGH to High Z [8,12, 13] CE LOW to Power-Up
[14] [8]
CE HIGH to Power-Down[8] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start R/W Pulse Width Data Set-Up to Write End Data Hold from Write End R/W LOW to High Z[13] R/W HIGH to Low Z[13]
WRITE CYCLE
15
Shaded area contains preliminary information. Notes: 10. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOL/IOH, and 30-pF load capacitance. 11. AC Test Conditions use VOH = 1.6V and VOL = 1.4V. 12. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 13. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady state voltage. 14. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
4
CY7C130/CY7C131 CY7C140/CY7C141
Switching Characteristics Over the Operating Range[5,10] (continued)
7C131-15 7C141-15 Parameter BUSY/INTERRUPT TIMING tBLA tBHA tBLC tBHC tPS tWB[16] tWH tBDD tDDD tWDD BUSY LOW from Address Match BUSY HIGH from Address Mismatch[15] BUSY LOW from CE LOW BUSY HIGH from CE HIGH[15] Port Set Up for Priority R/W LOW after BUSY LOW R/W HIGH after BUSY HIGH BUSY HIGH to Valid Data Write Data Valid to Read Data Valid Write Pulse to Data Delay 5 0 13 15 Note 17 Note 17 15 15 15 15 15
[15] [3]
7C130-25[3] 7C131-25 7C140-25 7C141-25 Min. Max. 20 20 20 20 5 0 20 25 Note 17 Note 17 25 25 25 25 25
7C130-30 7C131-30 7C140-30 7C141-30 Min. Max. 20 20 20 20 5 0 30 30 Note 17 Note 17 25 25 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns
Description
Min.
Max. 15 15 15 15
INTERRUPT TIMING tWINS tEINS tINS tOINR tEINR R/W to INTERRUPT Set Time CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset Time[15] CE to INTERRUPT Reset Time[15] ns ns ns ns ns ns
tINR Address to INTERRUPT Reset Time 15 25 25 Shaded area contains preliminary information. Notes: 15. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 16. CY7C140/CY7C141 only. 17. A write operation on Port A, where Port A has priority, leaves the data on Port B's outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B's address is toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read.
Switching Characteristics Over the Operating Range[5,10]
7C130-35 7C131-35 7C140-35 7C141-35 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid
[11]
7C130-45 7C131-45 7C140-45 7C141-45 Min. 45 Max.
7C130-55 7C131-55 7C140-55 7C141-55 Min. 55 Max. Unit ns 55 0 55 25 3 25 5 25 0 35 ns ns ns ns ns ns ns ns ns ns
Description
Min. 35
Max.
35 0 35 20 3 20 5 20 0 35 0 5 3 0
45 45 25 20 20 35
Data Hold from Address Change CE LOW to Data Valid OE LOW to Low Z
[11]
OE LOW to Data Valid[11]
[8,12, 13]
OE HIGH to High Z[8,12, 13] CE LOW to Low Z[8,12, 13] CE HIGH to High Z[8,12, 13] CE LOW to Power-Up[8] CE HIGH to Power-Down[8]
5
CY7C130/CY7C131 CY7C140/CY7C141
Switching Characteristics Over the Operating Range[5,10] (continued)
7C130-35 7C131-35 7C140-35 7C141-35 Parameter WRITE CYCLE[14] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE tBLA tBHA tBLC tBHC tPS tWB[16] tWH tBDD tDDD tWDD Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start R/W Pulse Width Data Set-Up to Write End Data Hold from Write End R/W LOW to High Z
[13]
7C130-45 7C131-45 7C140-45 7C141-45 Min. 45 35 35 2 0 30 20 0 Max.
7C130-55 7C131-55 7C140-55 7C141-55 Min. 55 40 40 2 0 30 20 0 Max. Unit ns ns ns ns ns ns ns ns 25 0 ns ns 30 30 30 30 5 0 35 ns ns ns ns ns ns ns 45 Note 17 Note 17 45 45 45 45 45 45 ns ns ns
Description
Min. 35 30 30 2 0 25 15 0
Max.
20 0 20 20 20 20 5 0 30 35 Note 17 Note 17 25 25 25 25 25 25 5 0 35 0
20
R/W HIGH to Low Z[13] BUSY LOW from Address Match BUSY HIGH from Address Mismatch[15] BUSY LOW from CE LOW BUSY HIGH from CE HIGH[15] Port Set Up for Priority R/W LOW after BUSY LOW R/W HIGH after BUSY HIGH BUSY HIGH to Valid Data Write Data Valid to Read Data Valid Write Pulse to Data Delay
BUSY/INTERRUPT TIMING 25 25 25 25
45 Note 17 Note 17 35 35 35 35 35 35
INTERRUPT TIMING tWINS tEINS tINS tOINR tEINR tINR R/W to INTERRUPT Set Time CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset Time[15] CE to INTERRUPT Reset Time[15] Address to INTERRUPT Reset Time[15] ns ns ns ns ns ns
Switching Waveforms
Read Cycle No.1
[18, 19]
Either Port Address Access
tRC
ADDRESS tOHA DATA OUT PREVIOUS DATAVALID tAA DATA VALID
C130-7
Notes: 18. R/W is HIGH for read cycle. 19. Device is continuously selected, CE = VIL and OE = VIL.
6
CY7C130/CY7C131 CY7C140/CY7C141
Switching Waveforms (continued)
Read Cycle No. 2 [18, 20]
CE OE tACE tDOE tHZOE tHZCE
Either Port CE/OE Access
tLZOE tLZCE DATA OUT tPU ICC ISB
DATA VALID tPD
C130-8
Read Cycle
No.3 [19]
Read with BUSY, Master: CY7C130 and CY7C131
tRC
ADDRESSR R/WR DINR
ADDRESS MATCH tPWE tHD VALID
ADDRESSL tPS BUSYL tBLA DOUTL
ADDRESS MATCH
tBHA tBDD VALID tWDD tDDD
C130-9
Write Cycle No.1 (OE Three-States Data I/Os - Either Port) Either Port
tWC ADDRESS tSCE CE tSA R/W tAW
[14, 21]
tPWE
tHA
tSD DATA IN DATA VALID
tHD
OE tHZOE HIGH IMPEDANCE DOUT
C130-10
Notes: 20. Address valid prior to or coincident with CE transition LOW. 21. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD.
7
CY7C130/CY7C131 CY7C140/CY7C141
Switching Waveforms (continued)
Write Cycle No. 2 (R/W Three-States Data I/Os - Either Port)
tWC ADDRESS tSCE CE tSA R/W tSD DATA IN tHZWE DATA OUT
C130-11
[15, 22]
tHA
tAW
tPWE
tHD
DATA VALID tLZWE HIGH IMPEDANCE
Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First:
ADDRESSL,R CEL tPS CER tBLC BUSYR tBHC ADDRESS MATCH
C130-12
CER Valid First:
ADDRESS L,R CER tPS CEL
ADDRESS MATCH
tBLC BUSYL
tBHC
C130-13
Note: 22. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
8
CY7C130/CY7C131 CY7C140/CY7C141
Switching Waveforms (continued)
Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First:
tRC or tWC ADDRESS MATCH ADDRESSL tPS ADDRESS MISMATCH
ADDRESS R tBLA BUSYR tBHA
C130-14
Right Address Valid First:
tRC or tWC ADDRESS MATCH ADDRESSR tPS ADDRESS MISMATCH
ADDRESSL tBLA BUSYL
C130-15
tBHA
Busy Timing Diagram No. 3 Write with BUSY (Slave:CY7C140/CY7C141)
CE
tPWE R/W
tWB BUSY
tWH
C130-16
9
CY7C130/CY7C131 CY7C140/CY7C141
Switching Waveforms (continued)
Interrupt Timing Diagrams Left Side Sets INTR
ADDRL tINS CEL tEINS R/WL tSA INTR tWINS tWC WRITE 3FF tHA
Right Side Clears INTR
tRC ADDRR tHA CER tEINR R/WR OER tOINR INTR READ 3FF tINT
C130-17
C130-18
Right Side Sets INTL
t WC ADDRR tINS CER tEINS R/WR tSA INTL tWINS WRITE 3FE tHA
C130-19
Left Side Clears INTL
ADDRR tHA CEL tEINR R/WL OEL tOINR INTL
tRC READ 3FE tINR
C130-20
10
CY7C130/CY7C131 CY7C140/CY7C141
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA)
NORMALIZED SUPPLY CURRENT vs.SUPPLYVOLTAGE 1.4 NORMALIZED I CC , I SB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 I SB3 5.5 6.0 NORMALIZED I CC , I SB ICC 1.2 1.0 0.8 0.6 0.4 0.2 0.6 -55
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC
OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) VCC =5.0V TA =25C
VCC =5.0V VIN =5.0V ISB3 25 125
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
OUTPUT SINK CURRENT (mA)
NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA NORMALIZED t AA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA =25C 1.6 1.4 1.2 1.0
NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 140 120 100 80 60 40 20
OUTPUT SINK CURRENT vs.OUTPUT VOLTAGE
VCC =5.0V 0.8 0.6 -55
VCC =5.0V TA =25C 1.0 2.0 3.0 4.0
25
125
0 0.0
SUPPLYVOLTAGE (V)
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
TYPICAL POWER -ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED tPC 2.5 DELTA t AA (ns) 2.0 1.5 1.0 0.5 0.0 0 1.0 2.0 3.0 4.0 5.0 30.0 25.0 20.0 15.0 10.0 5.0 0
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED I CC
NORMALIZED I CC vs.CYCLETIME VCC =4.5V TA =25C VIN =0.5V 1.0
0.75
VCC =4.5V TA =25C 0 200 400 600 800 1000 0.50 10 20 30 40
SUPPLYVOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
11
CY7C130/CY7C131 CY7C140/CY7C141
Ordering Information
Speed (ns) 30 35 Package Name P25 P25 P25 P25 D26 P25 P25 D26 P25 P25 D26 Operating Range Commercial Industrial Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military
Ordering Code CY7C130-30PC CY7C130-30PI CY7C130-35PC CY7C130-35PI CY7C130-35DMB
Package Type 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP
45
CY7C130-45PC CY7C130-45PI CY7C130-45DMB
55
CY7C130-55PC CY7C130-55PI CY7C130-55DMB
Speed (ns) 15 25
Ordering Code CY7C131-15JC CY7C131-15NC CY7C131-25JC CY7C131-25NC CY7C131-25JI CY7C131-25NI
Package Name J69 N52 J69 N52 J69 N52 J69 N52 J69 J69 N52 J69 N52 J69 N52 J69 N52 J69 N52 J69 N52
Package Type 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack
Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
30
CY7C131-30JC CY7C131-30NC CY7C131-30JI
35
CY7C131-35JC CY7C131-35NC CY7C131-35JI CY7C131-35NI
45
CY7C131-45JC CY7C131-45NC CY7C131-45JI CY7C131-45NI
55
CY7C131-55JC CY7C131-55NC CY7C131-55JI CY7C131-55NI
Shaded area contains preliminary information.
12
CY7C130/CY7C131 CY7C140/CY7C141
Ordering Information (continued)
Speed (ns) 30 35 Ordering Code CY7C140-30PC CY7C140-30PI CY7C140-35PC CY7C140-35PI CY7C140-35DMB 45 CY7C140-45PC CY7C140-45PI CY7C140-45DMB 55 CY7C140-55PC CY7C140-55PI CY7C140-55DMB Speed (ns) 15 25 Package Name P25 P25 P25 P25 D26 P25 P25 D26 P25 P25 D26 Package Name J69 N52 J69 N52 J69 N52 J69 N52 J69 J69 N52 J69 N52 J69 N52 J69 N52 J69 N52 J69 N52 Package Type 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP Operating Range Commercial Industrial Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Ordering Code CY7C141-15JC CY7C141-15NC CY7C141-25JC CY7C141-25NC CY7C141-25JI CY7C141-25NI
Package Type 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack
30
CY7C141-30JC CY7C141-30NC CY7C141-30JI
35
CY7C141-35JC CY7C141-35NC CY7C141-35JI CY7C141-35NI
45
CY7C141-45JC CY7C141-45NC CY7C141-45JI CY7C141-45NI
55
CY7C141-55JC CY7C141-55NC CY7C141-55JI CY7C141-55NI
Shaded area contains preliminary information.
13
CY7C130/CY7C131 CY7C140/CY7C141
MILITARY SPECIFICATIONS Group A Subgroup Testing
DC Characteristics Parameter VOH VOL VIH VIL Max. IIX IOZ ICC ISB1 ISB2 ISB3 ISB4 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameter READ CYCLE tRC tAA tACE tDOE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD Parameter tBLA tBHA tBLC tBHC tPS tWINS tEINS tINS tOINR tEINR tINR BUSY TIMING tWB[23] tWH tBDD 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Subgroups
BUSY/INTERRUPT TIMING
Note: 23. CY7C140/CY7C141 only.
Document #: 38-00027-M
14
CY7C130/CY7C131 CY7C140/CY7C141
Package Diagrams
48-Lead (600-Mil) Sidebraze DIP D26
52-Lead Plastic Leaded Chip Carrier J69
15
CY7C130/CY7C131 CY7C140/CY7C141
Package Diagrams (continued)
48-Lead (600-Mil) Molded DIP P25
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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